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CDB43L22
3.2
SPDIF In to Stereo Speaker Out
The CS43L22’s stereo differential PWM speaker output performance can be tested by loading the “SPDIF
In to Stereo Speaker Out” quick setup file provided with the software package. The script configures the
digital clock and data signal routing on the board as shown in Figure 2 .
Stereo output jacks J6 and J18 can be used to monitor filtered PWM output for measurement purposes. The
figure shows how a real speaker or a speaker model should attach to the binding posts during performace
tests. Digital S/PDIF input can be provided on the optical (OPT2) or RCA (J68) jacks. Refer to Section 4 on
page 11 for details on software configuration.
CS43L22
MCLK
LRCK
SCLK
SDIN
FPGA
CS8416
S/PDIF Rx
RX.RMCK
RX.LRCK
RX.SCLK
RX.SDOUT
S/PDIF
IN
(MASTER)
(SLAVE)
Pin 4 – SPKOUTA+
Pin 6 – SPKOUTA-
30 kHz filter for
measurement
J15
J6
Spkr A
15 μH
8 Ω
+
-
Measurement for
Ch. A
15 μH
Test Load
OR
Real
Speaker
Load
Pin 7 – SPKOUTB+
Pin 9 – SPKOUTB-
J19
30 kHz filter for
Spkr B
15 μH
8 Ω
15 μH
measurement
J18
+
-
Measurement for
Ch. B
Figure 2. SPDIF In to Stereo Speaker Out
Table 2 shows the expected performance characteristics one should expect when using the CDB43L22 for
SPDIF In to Stereo Speaker Out measurements.
Plot
FFT - S/PDIF In to Speaker Out @ 0 dBFS
FFT - S/PDIF In to Speaker Out @ -60 dBFS
Frequency Response- S/PDIF In to Speaker Out
THD+N - S/PDIF In to Speaker Out
Location
Figure 25 on page 30
Figure 26 on page 30
Figure 27 on page 30
Figure 28 on page 30
THD+N vs. Output Power- S/PDIF In to Speaker Out Figure 29 on page 30
Table 2. SPDIF In to Stereo Speaker Out Performance Plots
DS792DB1
9
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